招聘信息
 人力资源
       

技术开发
 

●MPEG4/H.264/AVC算法设计:
MPEG4 高级开发工程师
应聘者应精通MPEG4 视频解压缩基本原理,精通c/c++,具团队合作精神
并应具有以下实际工作经验
1、MPEG4(或H.263) 开发,测试,并将其成功移植到DSP的经验
2、定点DSP(如TI C5000) 的软件开发,优化经验
3、基于嵌入式操作系统的应用软件开发经验
4、 VC++,CCS,MATLAB 等开发工具的使用经验
具有以上工作经验者高薪诚聘

●模拟电路设计:
Senior Analog Design Engineer/高级模拟电路设计工程师
Job description:
1、lead a Physical Design Team through the complete SOC backend flow.
2、be working on IO Processor/IO translator System-on-a-Chip (SoC) development projects.

Job Requirement:
1、BSEE/MSEE with experience ranging from 5-8 years having at least been involved in physical design for two to three multi-million Gate Count ASIC or mixed-signal projects from netlist to Tape-out.
2、Synthesis and Static Timing Analysis using Synopsys-DC or Primetime.
3、Formal Verification using Verplex-LEC or Formality.
4、Floor-Planning, P & R ,Physical Verification/DRC/LVS.
5、High performance analog macro block layout such as ADCs, DACs, PORs, PLLs and ESD padrings.
6、Power grid/IR/Clock Tree/Xtalk analysis and fix.
7、Strong English and Chinese Verbal and Written Communication Skills.

●数字电路设计:
Digital Circuit Design Engieer-数字电路设计工程师
Digital Circuit Design Engineer/Sr. Engineer
数字电路设计工程师/高级工程师
Job responsibilities
l、Deep sub-micron CMOS digital circuit design
CMOS 深亚微米数字电路设计.
2、Standard logic cells, memory design and IO cell design.
标准逻辑单元,存储电路设计及输入输出单元设计.
3、High-speed IO design
高速输入输出单元设计
4、Supervisor of layout design
指导版图设计。

5、Standard logic cells and memory characterization.
标准逻辑单元和存储电路的参数提取。

Requirements:
l、Degree of bachelor or above, major in EE
电子工程专业本科以上学历。
2、Minimum two-year relevant work experiences
两年以上相关工作经验。
3、One of EEPROM, High-speed IO, Interface design experience is preferred.
有EEPROM,高速IO,接口电路设计经验者优先。

● MCU、DSP设计:
Job Description:
Familiar with the stages of product development including specification, design, verification, synthesis, timing, test pattern generation, backend verification and silicon debug

Required Skills:
Preferred BSEE minimum 2+year or MSEE minimum 1+year experience designing digital IC;
Experience with ASIC design using Verilog and Synopsys Cadence verilog_XL, nc-sim Synopsys primetime, Design Compiler
Familiar of HDL programming, EDA tools and IC design process

●嵌入式软件设计:
Job Duties:
1、Program/debug video,audio,USB driver for windows 2003/XP/2000/98;
2、Write test tools for Windows 2003/XP/2000/98;
3、Write install shell for Windows 2003/XP/2000/98.

Quaifications:
1、BS or above is required;
2、Good at programming in C language;
3、Understand Windows OS kernel;
4、Research on Video/Audio is plus.

●版图设计:
IC版图设计工程师/IC layout Engineer
Familiar with Vitruoso, Assura/Calibre.A proven track record in the sucessful design and physical implementation of high performance, PLLs, high speed A/D and D/A converters, from concept to product introduction, is preferred. Experience of assist backend management is preferred
Physical Layout Engineer/Sr. Engineer
物理版图设计工程师/高级工程师
Job responsibilities
1、Deep sub-micron CMOS Layout design
CMOS 深亚微米版图设计。
2、Standard logic cells, memory design and IO Layout design.
标准逻辑单元,存储电路设计及输入输出单元版图设计。
3、Analog block, EEPROM, High-speed IO Layout design
模拟电路, EEPROM, 高速IO版图设计。
4、Layout Physical Verification.
版图物理验证。
Requirements:
l、Degree of bachelor or above, major in EE, CS, Physical, Automatic or related
电子工程, 计算机,物理, 自动化或相关专业大专及以上学历。
2、Minimum two-year relevant work experiences
两年以上相关工作经验。
3、Familiar with deep submicron process design rule.
熟悉深亚微米工艺设计规则。
4、Skill in DRC/LVS debugging.
有DRC/LVS 查错技能。
5、One of Analog block, EEPROM, High-speed IO layout experience is preferred.
有模拟电路, EEPROM, 高速IO版图设计任一经验者优先。

●硬件开发:

1,本科及以上学历,相关行业两年以上硬件开发经验,具有扎实的模拟、数字电路基础知识;
2,具有ARM、AVR系列单片机经验,熟练应用嵌入式开发工具和相关的硬件工具及仪器;
3,精通FPGA、DSP器件及其应用,有大型测试验证数字项目经验者优先;
4,熟悉底层开发,并有丰富的独立开发嵌入式项目的经验;
5,具备电路系统、信号处理、通信方面理论基础知识;有数字、模拟电路设计调试经验;
6,熟练使用Protel、PowerPCB、Cadence之一进行原理图和PCB设计者优先;
7,英语水平良好,思维敏捷、表达能力强,认真负责;具备良好的团队合作精神,责任心强。


 

 
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